Voltage reference circuit based on temperature compensation

ABSTRACT

The present invention pertains to a voltage reference circuit based on temperature compensation, comprising positive and negative temperature coefficient generating units, temperature compensation circuit, image circuit and voltage divider. In this circuit, Item T is compensated with Item T, and Item T ln(T) is compensated by Item T in (T), which features a well-targeted compensation performance. The circuit outputs a reference voltage with zero temperature coefficient, which is independent to T and T ln (T). The output voltage value could be defined by adjusting the ratio of resistance in voltage divider. The invention provides a voltage reference circuit featuring good compensation, zero temperature coefficient and adjustable output voltage. The invention has a better compensation than the conventional one and a fixed output voltage, and it totally eliminates the temperature coefficient. The invention has wide application in analog IC and digital/analog mixed IC.

TECHNICAL FIELD

The present invention relates to a voltage reference circuit,specifically a voltage reference circuit based on temperaturecompensation, applicable for analog IC's and ditigal-analog mixed IC'swhere reference voltage with low temperature coefficient is required.

BACKGROUND ART

A voltage reference circuit with low temperature coefficient is anessential part for analog IC. The circuit generates low temperaturecoefficient voltage by weighted summing of positive and negativetemperature coefficient voltages to reduce variation of the referencevoltage with temperature. The conventional voltage reference isgenerated by weighted summing of difference in PN junction voltages ofbipolar transistors with positive and negative temperature coefficients,as shown in FIG. 1 (the temperature coefficient of resistor isneglected), and operational amplifier AO enables voltages at g0 and f0)to be equal, as I_(C) _(Q10) R₃₀=I_(C) _(Q30) R₂₀, then:

$\begin{matrix}{V_{REF} = {V_{{BE}_{Q\; 10}} + {\Delta \; {V_{{BE}_{{Q\; 10},{Q\; 20}}} \cdot \frac{R_{20}}{R_{10}}}}}} & (1)\end{matrix}$

Where V_(BE) is PN junction voltage of bipolar transistor Q10, andΔV_(BE) _(Q10,Q20) is the PN junction voltage difference between Q10 andQ20.

$\begin{matrix}{V_{BE} = {{V_{T}\ln \; \left( \frac{I_{C}}{I_{S}} \right)} = {\frac{kT}{q}{\ln\left( \frac{I_{C}}{b \cdot T^{2.5} \cdot ^{\frac{- E_{g}}{kT}}} \right)}}}} & (2)\end{matrix}$

Where k is Boltzmann constant, T is absolute temperature, q is thequantity of electron, I_(C) is the collector current of bipolartransistor, b is a proportional coefficient and E_(g) is Si bandgapenergy.

From Equation (2), the following could be derived:

$\begin{matrix}\begin{matrix}{{\Delta \; V_{{BE}_{{Q\; 10},{Q\; 20}}}} = {{V_{T}{\ln \left( \frac{I_{C_{Q\; 10}}}{I_{S}} \right)}} - {V_{T}{\ln \left( \frac{I_{C_{Q\; 20}}}{n_{0}I_{S}} \right)}}}} \\{= {V_{T}{\ln \left( {n_{0}\frac{I_{C_{Q\; 10}}}{I_{C_{Q\; 20}}}} \right)}}} \\{= {\frac{k\; {\ln \left( {n_{0}\frac{R_{20}}{R_{30}}} \right)}}{q} \cdot T}}\end{matrix} & (3)\end{matrix}$

Where k is Boltzmann constant, T is absolute temperature, q is thequantity of electron, n₀ is the ratio of the number of bipolartransistor Q20 to Q10.

From Equation (2) & (3), the following could be derived:

$\begin{matrix}{{V_{{BE}_{Q\; 10}} = {\frac{E_{g}}{q} + {\frac{kT}{q}{\ln \left( I_{C_{Q\; 10}} \right)}} - {\frac{2.5k}{q}T\; {\ln (T)}} - {\frac{k\; {\ln (b)}}{q}T}}}{Where}} & (4) \\{{I_{C_{Q\; 10}} = {\frac{I_{C_{Q\; 20}}R_{20}}{R_{30}} = {{\frac{\Delta \; V_{{BE}_{{Q\; 10},{Q\; 20}}}}{R_{10}} \cdot \frac{R_{20}}{R_{30}}} = {\frac{{kR}_{20}{\ln \left( {n_{0}\frac{R_{20}}{R_{30}}} \right)}}{{qR}_{10}R_{30}} \cdot T}}}}{{Then},}} & (5) \\{V_{{BE}_{Q\; 10}} = {\frac{E_{g}}{q} + {\frac{k\; {\ln\left( \frac{{kR}_{20}{\ln \left( {n_{0}\frac{R_{20}}{R_{30}}} \right)}}{{qbR}_{10}R_{30}} \right)}}{q} \cdot T} - {{\frac{1.5k}{q} \cdot T}\; {\ln (T)}}}} & (6)\end{matrix}$

From Equations (1),(3) and (6):

$\begin{matrix}{V_{REF} = {\frac{E_{g}}{q} + {\frac{k\; {\ln\left( \frac{{{kR}_{20}\left( {n_{0}\frac{R_{20}}{R_{30}}} \right)}^{\frac{R_{20}}{R_{10}}}{\ln \left( {n_{0}\frac{R_{20}}{R_{30}}} \right)}}{{qbR}_{10}R_{30}} \right)}}{q} \cdot T} - {{\frac{1.5k}{q} \cdot T}\; {\ln (T)}}}} & (7)\end{matrix}$

It can be seen from Equations (3) and (6), ΔV_(BE) _(Q10,Q20) is relatedto T, and V_(BE) _(Q10) is not only relevant to T, but also to T ln(T).Therefore, when ΔV_(BE) _(Q10,Q20) is added to V_(BE) _(Q10) , onlyT-related item can be used to compensate for T ln(T)-related item, asshown in Equation (7). For conventional voltage reference circuits, thereference voltage V_(REF) is always associated to T and T ln(T), whichmeans that the temperature coefficient of the reference voltage cannever be fully eliminated. Temperature coefficient of the conventionalvoltage reference source using standard process technology is 40 ppm/°C., namely, in the temperature range from −40° C. to 85° C., variationof the reference voltage can be calculated from:

40 ppm/° C.×[85° C.−(−40° C.)]×100%=0.5% .

Therefore, a voltage reference circuit with zero-temperature coefficientbased on temperature compensation is required to eliminate effects of Tand T ln(T) and solve the problem of inability of temperaturecoefficient elimination due to the dependence of output referencevoltage from the conventional voltage reference source on T and T ln(T).

Contents of Invention

The object of the present invention is to eliminate effects of T and Tln(T) and generate reference voltage with zero-temperature coefficientbased on temperature compensation, so as to solve the problem ofinability of temperature coefficient elimination due to the dependenceof output reference voltage from the conventional voltage referencesource on T and T ln(T).

The present invention accomplishes the object in the following way:

The present invention presents a voltage reference circuit based ontemperature compensation, which comprises a positive temperaturecoefficient generating unit, a negative temperature coefficientgenerating unit, temperature compensaion circuit, mirror circuit andvoltage divider circuit;

The positive temperature coefficient generating unit generates apositive temperature coefficient voltage with Item T ln (T), and outputsa positive temperature coefficient current with both Items T and T In(T);

The negative temperature coefficient generating unit generates positivetemperature coefficient voltage with both Items T and T ln (T), andoutputs positive temperature coefficient current with Item T;

The temperature compensation circuit converts the positive temperaturecoefficient current with both Items T and T ln (T) into positivetemperature coefficient voltage with both Items T and T ln (T), andcompensates the negative temperature coefficient voltage with both ItemsT and T ln (T) from negative temperature coefficient generating unit.The negative temperature coefficient generating unit, together withtemperature compensation circuit, generates reference voltage with zerotemperature coefficient;

Where T is absolute temperature;

The mirror circuit multiplies output current from the negativetemperature coefficient generating unit by a factor of m, which is theninput to the positive temperature coefficient generating unit;

The voltage divider adjusts output voltage and defines operating voltageof both positive and negative temperature coefficient generating units.

Furthermore, the temperature compensation circuit comprises resistor R5,the positive temperature coefficient generating unit comprisesoperational amplifier A1, bipolar transistors Q3 and Q4, resistors R6and R4, where the positive input of A1 is connected to the base of Q4,while the negative input of A1 is connected to the collector of Q4, andthe output of A1 is connected to the emitter of Q4, one end of R6 isconnected to the negative input of A1 and the collector of Q4, and theother end of R6 is grounded, between emitters of both Q4 and Q3 is R4,the collector of Q3 is connected to mirror circuit, and the base of Q3is connected to the base of Q4;

Furthermore, the negative temperature coefficient generating unitcomprises operational amplifier A2, bipolar transistors Q1 and Q2, andresistors R1, R2 and R3, where the emitter of Q1 is connected to thepositive input of A2, which is connected to R3, the emitter of Q2 isconnected via R1 with the negative input of A2, which is connected toR2, the output of A2 is connected to resistor R5, of which the other endis connected with R2 and R3, the other end of R2 is connected to theemitter of Q3, collectors of both Q1 and Q2 are connected with mirrorcircuit, and the output of A2 is connected to voltage divider;

Furthermore, the mirror circuit comprises the first NMOS transistor M1and the second NMOS transistor M2, of which the sources are grounded,the gates of both M1 and M2 are connected together, the gate of M2 isconnected to its drain, the drain of Ml is connected to the collector ofQ3, and the gate of M2 is connected to collectors of both Q1 and Q2;

Furthermore, the voltage divider comprises resistors R7 and R8, where R8is connected with the output of operational amplifier A2, while theother end of R8 is connected with R7 and bases of Q1, Q2, Q3 and Q4, theother end of R7 is connected to the sources of M1 and M2, and theconnection nodes of operational amplifier A2 with R5 and R8 are theoutput ports, Vo, of the voltage reference circuit;

Furthermore, the output reference voltage value is determined by theratio of R7 to R8: V_(o)=(E_(g)/q)·(1+R₇/R₈) where (E_(g)/q) is Sibandgap voltage. Different output reference voltages can be obtained byadjusting the ratio of R7 to R8.

Furthermore, R4 and R5 has the following relation:

${\frac{R_{5}}{R_{4}} = \frac{3}{2}};$

Furthermore, the negative temperature coefficient generating unitcomprises at least one bipolar transistor Q1 and at least one bipolartransistor Q2, and the ratio of the number of Q2 to Q1 is n. Thepositive temperature coefficient generating unit comprises at least onebipolar transistor Q3 and at least one bipolar transistor Q4, and theratio of the number of Q4 to Q3 is p. The mirror circuit comprises atleast one first NMOS transistor M1 and one second NMOS transistor M2,where n>1 and p>1.

Compared with the conventional voltage reference source, the voltagereference circuit based on temperature compensation in this inventionfeatures:

1. The conventional voltage reference uses Item T to compensate Item Tln(T), while the present invention uses Item T to compensate Items T,and T ln (T) to compensate T ln (T), which makes the compensation morespecific.

2. In the conventional voltage reference circuit, Item T ln(T) iscompensated by Item T, so the output reference voltage is ralated toboth T and T ln(T), which makes it impossible to completely eliminatetemperature coefficient (about 40 ppm/° C.). The present inventionoutputs a reference voltage independent to T and T ln(T), so, it iscapable of delivering a reference voltage with zero-temperaturecoefficient.

3. The output voltage range of the conventional voltage referencecircuit is the bandgap voltage of silicon, therefore, the output voltageis a fixed value. The present invenion offers a voltage referenceV_(o)=(E_(g)/q)·(1+R₇/R₈), which is defined flexibly by adjusting theratio of resistor R7 to R8, so the circuit is capable of delivering anyoutput voltage value within a certain range.

To sum up, the present invention has the advantages of well-targetedcompensation, zero-temperature coefficient and adjustable output voltagevalues.

Other advantages, objects and features of the present invention will beelaborated in the subsequent embodiments, and may be best understood byreferring to the following description of the presently preferredembodiments, together with the accompanying drawings.

DESCRIPTION OF DRAWINGS

To better understand the objects, technologies and advantages of thepresent invention, the accompanying drawings are referred to for furtherdescription, wherein:

FIG. 1 is a diagram of the conventional voltage reference circuit;

FIG. 2 is a diagram of Embodiment 1 of the voltage reference circuitbased on temperature compensation in the present invention;

FIG. 3 is a diagram of Embodiment 2 of the voltage reference circuitbased on temperature compensation in the present invention;

FIG. 4 is a diagram of Embodiment 3 of the voltage reference circuitbased on temperature compensation in the present invention;

FIG. 5 is a diagram of embodiment 4 of the voltage reference circuitbased on temperature compensation in the present invention.

SPECIFIC MODE FOR CARRYING OUT THE INVENTION

The embodiments of the present invention are described in detail andillustrated with attached drawings. It should be understand thefollowing embodiments are only intended to illustrate the invention, notto limit the claims.

Embodiment 1

FIG. 2 is the diagram of Embodiment 1 of the voltage reference circuitbased on temperature compensation in the present invention, as shown inFIG. 2: the present invention provides a voltage reference circuit basedon temperature compensation, comprising a positive temperaturecoefficient generating unit 1, a negative temperature coefficientgenerating unit 2, a temperature compensation circuit 3, mirror circuit4 and a voltage divider 5;

The positive temperature coefficient generating unit 1 generates apositive temperature coefficient voltage with Item T ln(T) and outputs apostive temperature coefficient current with Items T and T ln(T);

The negative temperature coefficient generating unit 2 generates anegative temperature coefficient voltage with Items T and T ln (T) andoutputs a positive temperature coefficient current with Item T;

The temperature compensation circuit 3 converts the positive temperaturecoefficient current with Items T and T ln (T) into positive temperaturecoefficient voltage with Items T and T ln (T) and compensates thenegative temperature coefficient voltage with Items T and T ln (T) fromnegative temperature coefficient generating unit. The negativetemperature coefficient generating unit works together with temperaturecompensation circuit to generate reference voltage with zero temperaturecoefficient;

Where, T is absolute temperature;

The mirror circuit 4 multiplies the output current from the negativetemperature coefficient generating unit by a factor of m, which is theninput to the positive temperature coefficient generating unit;

The voltage divider 5 adjusts output voltage and defines operatingvoltages of both positive and negative temperature coefficientgenerating units.

As further improvements for above embodiment, the temperaturecompensation circuit comprises resistor R5, the positive temperaturecoefficient generating unit comprises operational amplifier Al, bipolartransistors Q3 and Q4, and resistors R6 and R4, wherein the positiveinput of A1 is connected to the base of Q4, the negative input of A1 isconnected to the collector of Q4, the output of A1 is connected to theemitter of Q4, one end of R6 is connected to the negative input of A1and the collector of Q4, and the other end of R6 is grounded, In betweenemitters of Q4 and Q3 is R4, the collector of Q3 is connected to mirrorcircuit, and the base of Q3 is connected with the base of Q4;

As further improvements for above embodiment, the negative temperaturecoefficient generating unit comprises operational amplifier A2, bipolartransistors Q1 and Q2, resistors R1, R2 and R3, wherein the emitter ofQ1 is connected to the positive input of A2, which is connected to R3,the emitter of Q2 is connected via R1 with the negative input of A2,which is connecte to R5, and the other end of R5 is connected to R2 andR3, the other end of R2 is connected to the emitter of Q3, thecollectors of Q1 and Q2 are connected with mirror circuit, and theoutput of A2 is connected to voltage divider circuit;

As further improvements for above embodiment, the mirror circuitcomprises first NMOS transistor M1 and second NMOS transistor M2,wherein the source of M1 and M2 are grounded, the gate of M1 isconnected to the gate of M2, the gate of M2 is connected to the drain ofM2, the drain of M1 is connected with the collector of bipolartransistor Q3, and the gate of M2 is connected with collectors ofbipolar transistors Q1 and Q2;

As further improvements for above embodiment, the voltage dividercomprises resistors R7 and R8, wherein R8 is connected to the output ofA2, the other end of R8 is connected to R7 and also to the base of Q1,Q2, Q3 and Q4, the other end of R7 is connected to the source of M1 andM2, the connectiong node of A2 with R5 and R8 is the output port, Vo, ofthe reference circuit;

As further improvements for above embodiment, the output referencevoltage value is determined by the ratio of R7 to R8:V_(o)=(E_(g)/q)·(1+R₇/R₈) where (E_(g)/q) is the bandgap voltage ofsilicon. Different output reference voltages can be obtained byadjusting the ratio of R7 to R8.

As further improvements for above embodiment, R4 and R5 has thefollowing relation:

${\frac{R_{5}}{R_{4}} = \frac{3}{2}};$

As further improvements for above embodiment, the negative temperaturecoefficient generating unit comprises at least one bipolar transistor Q1and at least one bipolar transistor Q2, wherein the ratio of the numberof Q2 to the number of Q1 is n. The positive temperature coefficientgenerating unit comprises at least one bipolar transistor Q3 and atleast one bipolar transistor Q4, wherein the ratio of the number of Q4to the number of Q3 is p. The mirror circuit comprises at least onefirst NMOS transistor M1 and at least one second NMOS transistor M2,wherein the ratio of the number of first MOS transistors M1 to thenumber of second NMOS transistor M2 is m, where n>1, p>1.

The present invention is described in detail, including its operationalprinciple and embodiments:

FIG. 2 shows a whole diagram of the present invention, including twoop-amps A1 and A2, four bipolar transitors Q1, Q2, Q3 and Q4, two MOStransostors M1 and M2 and eight resistors R1 to R8. Nodes a, b, c, d areconnections of the base of Q4, Q3, Q2 and Q1, respectively; Node e is acommon connection for R7 and R8, and it connects the base of Q4, Q3, Q2and Q1; Node f connects the positive input of A2 with the emitter of Q1,Node g is a meeting point connecting the negative input of A2 with R1and R1, Node h connects bipolar transistor Q4 to the negative input ofA1, Nnode i is the output pport of operational amplifier A2; Connectionsin FIG. 2 is identical with the description of the invention content,regardless of temperature coefficient of resistors and MOS transistors,the theory of operation is as follows:

The difference betweem PN junction voltage of bipolar transistors Q1 andQ2 results in a positive temperature coefficient voltage with Item T,the operational amplifier A2 causes voltages at Nodes f and g to beequal, so the voltage on R1 is:

$\begin{matrix}{V_{R\; 1} = {{\Delta \; V_{{{BE}\; 1},2}} = {{{V_{T}{\ln \left( \frac{I_{Q\; 1}}{I_{s}} \right)}} - {V_{T}{\ln \left( \frac{I_{Q\; 2}}{{nI}_{s}} \right)}}} = {{V_{T}{\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}} = {\frac{k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q} \cdot T}}}}} & (8)\end{matrix}$

Where n is the ratio of the number of bipolar transistor Q2 to thenumber of bipolar transistor Q1.

The difference between PN junction voltage of bipolar transistors Q3 andQ4 results in a positive temperature coefficient voltage with Items Tand T ln(T), e.g. voltage on R4:

$\begin{matrix}{V_{R\; 4} = {{\Delta \; V_{{{BE}\; 3},4}} = {{V_{T}{\ln \left( {p \cdot \frac{I_{Q\; 3}}{I_{Q\; 4}}} \right)}} = {\frac{kT}{q}{\ln \left( {p \cdot \frac{I_{Q\; 3}}{I_{Q\; 4}}} \right)}}}}} & (9)\end{matrix}$

Operational amplifier Al makes voltages at Nodes a and h equal,neglecting the base current of all bipolar transistors, the voltage onR6 is:

$\begin{matrix}{{V_{R\; 6} = {V_{R\; 7} = {\frac{R_{7}}{R_{8} + R_{7}} \cdot V_{O}}}}{{Then},}} & (10) \\{I_{Q\; 4} = {I_{R\; 6} = {\frac{R_{7}}{\left( {R_{8} + R_{7}} \right)R_{6}} \cdot V_{O}}}} & (11)\end{matrix}$

The current mirror consisting of the first NMOS transistor M1 and secondNMOS transistor M2 multiplies the sum of current at collectors ofbipolar transistors Q1 and Q2 by a factor of m, which is used as thecollector current of bipolar transistor Q3:

$\begin{matrix}{I_{Q\; 3} = {{m \cdot \left( {I_{Q\; 1} + I_{Q\; 2}} \right)} = {{m \cdot \left( {1 + \frac{R_{2}}{R_{3}}} \right)}I_{Q\; 2}}}} & (12)\end{matrix}$

According to Equation (8):

$\begin{matrix}{I_{Q\; 2} = {\frac{V_{R\; 1}}{R_{1}} = {\frac{k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}} \cdot T}}} & (13)\end{matrix}$

According to Equations (12) and (13):

$\begin{matrix}{{I_{Q\; 3} = {{\frac{m \cdot k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}} \cdot \left( {1 + \frac{R_{2}}{R_{3}}} \right) \cdot T} = {\alpha_{1} \cdot T}}}{Where}} & (14) \\{\alpha_{1} = {\frac{m \cdot k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}} \cdot \left( {1 + \frac{R_{2}}{R_{3}}} \right)}} & (15)\end{matrix}$

According to Equations (9), (11) and (14):

$\begin{matrix}{I_{R\; 4} = {\frac{V_{R\; 4}}{R_{4}} = {{{\frac{k}{{qR}_{4}}\left\lbrack {{\ln \left( \frac{\alpha_{1} \cdot p \cdot R_{6} \cdot \left( {R_{8} + R_{7}}\; \right)}{R_{7} \cdot V_{O}} \right)} + {\ln (T)}} \right\rbrack} \cdot T} = {{\alpha_{2} \cdot T} + {{\alpha_{3} \cdot T}\; {\ln (T)}}}}}} & (16) \\{\mspace{20mu} {Where}} & \; \\{\mspace{20mu} {\alpha_{2} = {\frac{k}{{qR}_{4}} \cdot {\ln \left( \frac{\alpha_{1} \cdot p \cdot R_{6} \cdot \left( {R_{8} + R_{7}} \right)}{R_{7} \cdot V_{O}} \right)}}}} & (17) \\{\mspace{20mu} {\alpha_{3} = \frac{k}{{qR}_{4}}}} & (18)\end{matrix}$

According to Equations (12), (14) and (16), the current on R5 is:

$\begin{matrix}{I_{R\; 5} = {{I_{Q\; 1} + I_{Q\; 2} + I_{Q\; 3} + I_{R\; 4}} = {{\left( {{\frac{m + 1}{m} \cdot \alpha_{1}} + \alpha_{2}} \right) \cdot T} + {{\alpha_{3} \cdot T}\; {\ln (T)}}}}} & (19)\end{matrix}$

Bipolar transistor Q1 generates a PN junction voltage with negativetemperature coefficient containing Items T and T ln (T). According toEquation (4), the PN junction voltage of bipolar transistor Q1 is:

$\begin{matrix}{{V_{{BE}_{Q\; 1}} = {{V_{T}{\ln \left( \frac{I_{Q\; 1}}{I_{s}} \right)}} = {\frac{E_{g}}{q} + {\frac{kT}{q}{\ln \left( I_{Q\; 1} \right)}} - {\frac{2.5k}{q}T\; {\ln (T)}} - {\frac{k\; {\ln (b)}}{q}T}}}}\mspace{20mu} {Where}} & (20) \\{\mspace{20mu} {{I_{Q\; 1} = {\frac{R_{2}}{R_{3}}I_{Q\; 2}}}\mspace{20mu} {{The}\mspace{14mu} {voltage}\mspace{14mu} {on}\mspace{14mu} R\; 8\mspace{14mu} {is}\text{:}}}} & (21) \\{\mspace{20mu} {V_{R\; 8} = {{V_{{BE}_{Q\; 1}} + V_{R\; 3} + V_{R\; 5}} = {V_{{BE}_{Q\; 1}} + {I_{Q\; 2} \cdot R_{2}} + {I_{R\; 5} \cdot R_{5}}}}}} & (22)\end{matrix}$

Where V_(R3) is the positive temperature coefficient voltage for R3, andV_(R5) is the positive temperature coefficient voltage containing ItemsT and T ln (T).

According to Equations (13) and (19)-(22),

$\begin{matrix}\begin{matrix}{V_{R\; 8} = {\frac{E_{g}}{q} + {\frac{k}{q}{{\ln\left( {\frac{R_{2}}{R_{3}}\frac{k \cdot {l\left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}}} \right)} \cdot T}} - {{\frac{1.5k}{q} \cdot T}\; {\ln (T)}} - {\frac{k\; {\ln (b)}}{q} \cdot T} +}} \\{{{R_{2}\; {\frac{k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}} \cdot T}} + {\left( {{\frac{m + 1}{m} \cdot \alpha_{1}} + \alpha_{2}} \right) \cdot R_{5} \cdot T} + {\alpha_{3} \cdot R_{5} \cdot}}} \\{{T\; {\ln (T)}}} \\{= {\frac{E_{g}}{q} + {\begin{Bmatrix}\begin{matrix}{{\frac{k}{q}{\ln\left( {\frac{R_{2}}{R_{3}}\frac{k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3\;}}} \right)}}{q \cdot R_{1}}} \right)}} -} \\{\frac{k\; {\ln (b)}}{q} + {R_{2}\; \frac{k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}}} +}\end{matrix} \\{\left( {{\frac{m + 1}{m} \cdot \alpha_{1}} + \alpha_{2}} \right) \cdot R_{5}}\end{Bmatrix} \cdot T} +}} \\{{{\left\{ {{- \frac{1.5k}{q}} + {\alpha_{3} \cdot R_{5}}} \right\} \cdot T}\; {\ln (T)}}}\end{matrix} & (23)\end{matrix}$

To make V_(R8) independent to temperature, coefficients before T and Tln (T) should be 0, then:

$\begin{matrix}{{{\frac{k}{q}{\ln\left( {\frac{R_{2}}{R_{3\;}}\frac{k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}}} \right)}} - \frac{k\; {\ln (b)}}{q} + {R_{2}\frac{k \cdot {\ln \left( {n \cdot \frac{R_{2}}{R_{3}}} \right)}}{q \cdot R_{1}}} + {\left( {{\frac{m + 1}{m} \cdot \alpha_{1}} + \alpha_{2}} \right) \cdot R_{5}}} = 0} & (24) \\{\mspace{20mu} {{{- \frac{1.5k}{q}} + {\alpha_{3} \cdot R_{5}}} = 0}} & (25)\end{matrix}$

According to Equations (18) and (25),

$\begin{matrix}{\frac{R_{5}}{R_{4}} = \frac{3}{2}} & (26)\end{matrix}$

According to Equations (23), (18) and (25),

$\begin{matrix}{{V_{O} \cdot \frac{R_{8}}{R_{7} + R_{8}}} = {V_{R\; 8} = \frac{E_{g}}{q}}} & (27)\end{matrix}$

Where V_(o) is the compensated output reference voltage, and (E_(g)/q)is the bandgap voltage of silicon.

According to Equations (15), (17), (24) and (26),

$\begin{matrix}{{\ln \left( R_{1} \right)} = {{\ln \left( \frac{k \cdot r_{2,3} \cdot {l\left( {n \cdot r_{2,3}} \right)}}{q \cdot b} \right)} + {\frac{3}{2} \cdot {\ln \left\lbrack \frac{m \cdot p \cdot k \cdot {\ln \left( {n \cdot r_{2,3}} \right)} \cdot \left( {1 + r_{2,3}} \right) \cdot r_{6,1} \cdot r_{8,7}}{E_{g}} \right\rbrack}} + {r_{2,1} \cdot {\ln \left( {n \cdot r_{2,3}} \right)}} + {r_{5,1} \cdot \left( {m + 1} \right) \cdot \left( {1 + r_{2,3}} \right) \cdot {\ln \left( {n \cdot r_{2,3}} \right)}}}} & (28) \\{\mspace{20mu} {Where}} & \; \\{\mspace{20mu} {{r_{2,1} = \frac{R_{2}}{R_{1}}},{r_{5,1} = \frac{R_{5}}{R_{1}}},{r_{6,1} = \frac{R_{6}}{R_{1}}},{r_{2,3} = \frac{R_{2}}{R_{3}}},{r_{8,7} = \frac{R_{8}}{R_{7}}}}} & (29)\end{matrix}$

When resistor ratio coefficient in Equation (29) is defined(theoretically, the ratio in Equation (29) can be any value, which canbe chosen based on specific process for convenience of layout design),R₁ can be calculated using Equation (28). Resistance values of R₂, R₃,R₄, R₅ and R₆ are calculated by applying Equations (26) and (29).

The compensated output reference voltage is calculated using Equation(27):

$\begin{matrix}{V_{O} = {\frac{E_{g}}{q} \cdot \left( {1 + \frac{R_{7}}{R_{8}}} \right)}} & (30)\end{matrix}$

As shown in Equation (30), the V_(o) expression does not contain itemsrelevant to temperature T, so the compensated output reference voltagehas zero temperature coefficient; the compensated output referencevoltage V_(o) is determined by the ratio of R₇ to R₃. Therefore,different output reference voltages can be achieved by adjusting theratio of R₇ to R₈, where the value of R7 should be chosen such that M2operates in saturation region and bipolar transistors Q1 to Q4 operatein amplifying area. The voltage reference circuit based on temperaturecompensation in the present invention is fabricated in general Si-gateBiCMOS process.

Embodiment 2

FIG. 3 is a diagram of embodiment 2 of the present invention. As shownin FIG. 3, the difference between Embodiment 1 and Embodiment 2 is asfollows: resistor R1 connects the emitter of Q2, resistor R2 connectsthe collector of bipolar transistor Q2 and the drain of second MOStransistor M2, resistor R3 connects the collector of bipolar transistorQ1 and the drain of the second NMOS transistor M2, the positive input ofoperational amplifier A2 connects the collector of bipolar transistorQ1, and the negative input of operational amplifier A2 connects thecollector of Q2 and resistor R2.

Embodiment 3

FIG. 4 is a diagram of Embodiment 3 of the present invention. As shownin FIG. 4, the difference between Embodiment 3 and Embodiment 2 is asfollows: bipolar transistors Q1,Q2,Q3 and Q4 are NPN type; the first MOStransistor M1 and the second MOS transistor M2 are N-channel enhancedMOSFET, and the common connection for R5 and R7 are grounded.

Embodiment 4

FIG. 5 is a diagram of Embodiment 4 of the present invention. As shownin FIG. 5, the difference between Embodiment 4 and Embodiment 1 is asfollows: bipolar transistors Q1, Q2, Q3 and Q4 are NPN type; the firstMOS transistor M1 and the second MOS transistor M2 are N-channelenhanced MOSFET, and the common connection for R5 and R7 are grounded.

The foregoing preferred embodiments are provided to describe, not tolimit, technical approaches in the present invention. Obviously, bearingthe essence and concept of the present invention, technologists in thisfield can make various changes and modifications to the presentinvention. It should be understood that those changes and modificationsare also covered by claims of the present invention, if they are withthe same purpose and within the same scope of the present invention.

What is claimed is:
 1. A temperature compensation based voltagereference circuit, comprising a positive temperature coefficientgenerating unit, a negative temperature coefficient generating unit, atemperature compensation circuit, mirro circuit and a voltage divider,wherein; A positive temperature coefficient generating unit generates apositive temperature coefficient voltage comprising Item T ln (T), andoutputs a positive temperature coefficient current comprising Items Tand T ln (T); A negative temperature coefficient generating unitgenerates a negative temperature coefficient voltage comprising Item Tln (T), and outputs a positive temperature coefficient currentcomprising Item T; A temperature compensation circuit converts apositive temperature coefficient current comprising Items T and T ln (T)into a positive temperature coefficient voltage comprising Items T and Tln (T), and compensates negative temperature coefficient voltagecomprising Items T and T ln(T) generated by negative temperaturecoefficient generating unit, which, together with temperaturecompensation circuit, generates a reference voltage with zerotemperature coefficient; Wherein, T is absolute temperature. A mirrocircuit multiplies output current from the negative temperaturecoefficient generating unit by a factor of m, which is then input intothe positive temperature coefficient generating unit; A voltage divideradjusts output voltage and calculates operating voltages of bothpositive and negative temperature coefficient generating units.
 2. Avoltage reference circuit based on temperature compensation according toclaim 1 features: A temperature compensation circuit comprising resistorR5, a positive temperature coefficient generating unit comprisingoperational amplifier A1, bipolar transistors Q3, Q4, resistors R6 andR4, wherein, the positive input of operational amplifier A1 is connectedto the base of Q4, and the negative input is connected to its collector,and the output of operational amplifier A1 is connected to the emitterof Q4, and one end of resistor R6 is connected to the negative input ofA1 and collector of Q4, the other end of R6 is grounded, and resistor R4is between emitter of Q4 and emitter of Q3, the collector of Q3 isconnected with mirro circuit, and the base of Q3 is connected to base ofQ4.
 3. A voltage reference circuit based on temperature compensationaccording to claim 2, features: a negative temperature coefficientgenerating unit comprising operational amplifier A2, bipolar transistorsQ1 and Q2, resistor R1,R2 and R3, where the emitter of Q1 is connectedto the positive input of A2, which is connected to R3, the emitter of Q2is connected via R1 to negative input of A2, which is connected to R2,the output of A2 is connected to R5, of which the other end is connectedto R2 and R3, and the other end of R2 is connected to the emitter of Q3,and collectors of Q1 and Q2 are connected with the other end of mirrorcircuit, and the output of A2 is connected to voltage divider.
 4. Avoltage reference circuit based on temperature compensation according toclaim 3 features: A mirror circuit comprising first NMOS transistor M1and second NMOS transistor M2, wherein the sources of the first MOStransistor M1 and second MOS transistor M2 are grounded, the gates of M1and M2 are connected with each other, the gate of M2 is connected to thedrain of M2, the drain of M1 is connected to the collector of Q3 and thegate of M2 is connected to collectors of Q1 and Q2.
 5. A voltagereference circuit based on temperature compensation according to claim 4features: A voltage divider comprising resistors R7 and R8, wherein R8is connected to the output of A2, and the other end of R8 is connectedto R7 and bases of Q1, Q2, Q3 and Q4, the other end of R7 is connectedto sources of M1 and M2, the connecting node of A2 with R5 and R8 is theoutput port of the reference circuit, Vo.
 6. A voltage reference circuitbased on temperature compensation according to claim 5 features: Areference voltage output Vo determined by the ratio of R₇ and R₈:V_(o)=(E_(g)/q)·(1+R₇/R₈), where (E_(g)/q) is the bandgap voltage ofsilicon, and different output reference voltages by adjusting the ratioof R7 and R8.
 7. A voltage reference circuit based on temperaturecompensation according to claim 6 features: R4 and R5 expressed as:$\frac{R_{5}}{R_{4}} = {\frac{3}{2}.}$
 8. A voltage reference circuitbased on temperature compensation according to claim 7 features: Anegative temperature coefficient generating unit comprising at least 1bipolar transistor Q1 and at least 1 bipolar transistor Q2, wherein theratio of the number of all Q2 to all Q1 is n; A positive temperaturecoefficient generating unit comprising at least 1 bipolar transistor Q3and and 1 bipolar transistor Q4, wherein the ratio of the number of allQ4 to all Q3 is p, where, n>1, p>1.